Digital delay lines are commonly used to “delay” or prevent a signal from arriving at an output until a predetermined time has elapsed. Each delay line typically contain several delay cells, with each of the delay cells having a fixed delay time. Delay time in delay lines is commonly changed by increasing or decreasing the number of delay cells that a signal passes through; as the number of delay cells increase, the overall delay time will increase, and vice versa.
Delay cells in delay lines have been connected in various ways. In some situations, delay cells have been connected in series, with an output for each delay cell coupled to a multiplexer, logic gates, or flip-flops, to select the output best synchronized with a reference clock. In other situations, a delay line may have single clock output, a digital control signal, and multiple delay cells connected in a lattice formation. In these situations, the multiple delay cells connected in a lattice formation are often NAND gates, and the digital control signal enables or disables different NAND gates in the lattice.
FIG. 1A shows an existing exemplary NAND gated-based delay line. The delay cells 10-N0 may be provided in a “lattice” configuration in which each delay cell provide a pair of selectable signal paths, each of which include various NAND gate-based delay elements. Each intermediate delay cell (for example, cell 20) may be connected to pair of neighboring cells via respective input/output terminals (IN-A/OUT-A1&A2 and IN-B1&B2/OUT-B). An input signal is presented from a “lower” neighboring cell 10 to the cell 20 at a first input terminal IN-A. The input signal is then coupled to a first input of NAND gates 27 & 28. Control signal SEL2 and/or inverted control signal SEL2 may be coupled to the second input of these NAND gates 27 & 28. The output of NAND gate 27 may be coupled to the output terminal OUT-B of the delay cell 20, which may be coupled to an input terminal of the next delay cell. The output of NAND gate 28 may be coupled to a first output terminal OUT-A1, which may be connected a first input of a NAND gate in a preceding delay cell, such as NAND gate 19. A third NAND gate 19 may have its input terminals coupled to input terminals IN-B1&B2 of the delay cell, which may in turn be coupled to the corresponding outputs of the next delay cell. The output of the third NAND gate 19 may be coupled to output terminal OUT-A2, which may be connected a second input of a NAND gate in a preceding delay cell, such as NAND gate 19. An input signal 15 may be coupled to an input terminal of a first delay, an output signal 45 may be coupled to the output of NAND gate 55 while the inputs of the NAND gate 55 may be coupled to corresponding output terminals of delay cell 10. An inverter 25 may be coupled between the output of NAND gate N7 and the input of the NAND gate N9 in the last delay cell N0.
By adjusting control signal values SEL1-SELN the path of signal propagation can be changed. Enabling additional NAND gates, such as NAND gates 17 and 27, while disabling others, such as NAND gates 18 and 28, will redirect the signal further down the lattice through additional NAND gates; each additional NAND gate that the signal passes through further delays the signal, increasing the total delay. Similarly, disabling these NAND gates in the lattice may reduce the number of NAND gates that the signal passes through, thereby reducing the delay.
One issue with using NAND gates as delay cells is that when a NAND gate is disabled and not used in the signal delay path, the NAND gate does not store any signal information. Because the NAND gate does not store any signal information, when a disabled NAND gate is later enabled, there may be a signal inconsistency and/or glitch between the time the NAND gate is first enabled and the time the NAND gate begins processing the signal.
There is a need for a configurable delay cell system where delay cells can be enabled and disabled without causing signal inconsistencies or glitches.